Nano-computing is based on the premise of switches that are of nanometer scale in the functional dimension(s). Examples of technology used in implementing nano-scale switches are disclosed and claimed in the following: U.S. Pat. No. 6,459,095, entitled “Chemically Synthesized and Assembled Electronic Devices”, issued to James R. Heath et al on Oct. 1, 2002; U.S. Pat. No. 6,314,019, entitled “Molecular Wire Crossbar Interconnect (MWCI) for Signal Routing and Communications”, issued to Philip J. Kuekes et al on Nov. 6, 2001; application Ser. No. 09/280,045, entitled “Molecular Wire Crossbar Logic (MWCL)”, filed on Mar. 29, 1999, in the names of Philip J. Kuekes et al; U.S. Pat. No. 6,128,214, entitled “Molecular Wire Crossbar Memory”, issued to Philip J. Kuekes et al on Oct. 3, 2000; and U.S. Pat. No. 6,256,767, entitled “Demultiplexer for a Molecular Wire Crossbar Network”, issued to Philip J. Kuekes et al on Jul. 3, 2001, all assigned to the same assignee as the present application.
To have fully general computing, one must have not only logic functions and memory functions, but we must be able to take a logical variable and put it into a memory and be able to reuse it as the input to another logic function. This allows one to build finite state machines and thus do completely general computing. One method of doing this is to use a latch.
While such a latch is well-known in the art of general computing, as that art has developed in the year 2003, advances in the art of nano-computing require new approaches to developing a latching functionality at the nanometer scale.
Thus, what is needed is a latch that is specifically configured for nanometer-scale computing and is compatible in size with nanometer scale logic.